The disclosure relates to the fabrication of integrated circuits and more particularly, to an interconnect structure and a process for forming the interconnect structure.
Integrated circuits are now transitioning from aluminum to copper metal interconnects as device generation goes beyond 0.25 micron design rules. Aluminum metal is limited for these design rules due to its inability to reliably carry current in smaller sized circuit lines. Copper has lower resistivity than aluminum so it can carry more current in smaller areas, thus enabling faster and denser chips with increased computing power. Moreover, the integration of copper reduces the number of interconnect levels required and consequently removes numerous processing steps which directly impact overall yield. Beyond the 0.25 micron generation of devices, current densities can reach levels that induce electromigration failure of traditional doped aluminum conductors. The increased electromigration resistance of copper relative to aluminum overcomes this limitation, which primarily impacts the finest pitch lines found at the lower interconnect levels.
Along with the transition to copper is the improvement upon the dielectric insulating layers. Silicon dioxide has been traditionally used as the primary material for insulators and has a dielectric constant of about 4.0. New insulating materials for interconnects, such as low k dielectrics, have been proposed, which lower interconnect capacitance and crosstalk noise to enhance circuit performance. The low k dielectric materials (a film having a low capacitance and a low resistance) that have been considered typically include materials containing Si, C, O and H and have a dielectric constant less than about 3.5. The low k materials may be polymeric or non-polymeric. Some examples of low k dielectrics include organosilicate glasses, methylsiloxane, methylsesquioxanes, hydrogen silsesquioxanes, polyimides, parylenes, fluorocarbons, benzocyclobutenes and other organic and inorganic materials.
Fabrication of integrated circuits using copper interconnects and low k dielectrics presents new challenges and problems for the semiconductor manufacturer. In order to make these devices, the manufacturers commonly use a damascene process. The damascene process uses most of the same chipmaking technologies to form the interconnect as the traditional structure but differs in the way in which the structure is built. Instead of etching a pattern in the metal film and surrounding it with a dielectric material, the damascene process typically includes etching a pattern into the dielectric film, then filling the pattern with copper. An advantage to the damascene process is that the metal etch is replaced with a simpler dielectric etch as the critical step that defines the width and spacing of the interconnect lines.
During a dual damascene process, there are typically four etches: via, trench, photoresist and polymer strip, and bottom barrier removal. Each has challenges irrespective of damascene strategy. For example, during the via etch, selectivity of the resist, selectivity of the bottom barrier and profile in the bottom of the via are critical. Key in the trench etch is maintaining the integrity of the bottom barrier while not impacting the desired lateral dimensions of the trench. With regard to photoresist and polymer removal, prior art ashing techniques can result in pullback of the dielectric film or may cause an increase in the effective k value of the dielectric film. Other problems include lithography and patterning of photoresists on the low k dielectric surface.
One of the methods used to directly etch or strip materials from semiconductor surfaces is a Reactive Ion Etch (RIE) plasma process. RIE is highly anisotropic and can be used to selectively etch a layer with well defined vertical walls. Such plasmas are formed within a carefully designed reactor chamber by the exposure of appropriate gases to radio frequency energy while controlling the bias voltage developed on the substrate. The gases must be chosen with specific consideration to the material desired to be etched. In particular, the product obtained from the reaction between the gas plasma and the material surface must be sufficiently volatile to be removed from the material surface by the reactor system. In the practice of reactive ion etching of a material surface, the reactive gases are introduced into a reactor chamber at reduced pressure. The chamber is then energized through the introduction of radio frequency (RF) energy, which allows the reactive gases to transform into reactive species which in turn can be used to selectively etch portions of the exposed surfaces.
Current RIE processes are generally problematic for use with the new low k dielectric materials. The new low k dielectrics typically contain carbon within its structure making these materials more resist-like. The presence of carbon has been found to reduce the selectivity for current RIE processes. A reduction in selectivity can affect the critical dimensions patterned into the dielectric. It is important to maintain a critical dimension (CD) for the various features patterned into the substrate within a tightly controlled specification as well as promote proper underlayer surface conditions so that additional layers may be deposited or formed. Small deviations in the patterned profiles formed in the underlayers can adversely impact device performance, yield and reliability of the final integrated circuit. Moreover, most current RIE plasmas typically are generated from oxygen-containing gases that are selective for removing traditional dielectrics, such as SiO2, relative to a photoresist mask. It has been found that these types of oxygen-containing plasmas readily damage certain low k materials used in advanced integrated circuit manufacture. Exposure of the low k materials to the oxygen-containing plasma can raise the dielectric constant of the low k dielectric underlayers during plasma processing. The increases in dielectric constant affects, among others, interconnect capacitance, which directly impacts device performance.
The process of removing the photoresist mask, polymers and post etch residues after the features have been etched into the substrate is generally known as stripping or ashing. The stripping or ashing process must exhibit high selectivity since small deviations in the etched profiles can adversely impact device performance, yield and reliability of the final integrated circuit. Since most of the new low k dielectrics contain carbon within their structure, current processes exhibit reduced selectivity. Moreover, the current processes for ashing or stripping photoresist from new low k dielectric materials can result in pullback of the dielectric film and/or cause an increase in the effective k value of the dielectric film.
A method of forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a barrier layer of a substrate, wherein first layer has a dielectric constant higher than the second layer. The second layer is selected from a low k dielectric material comprising Si, C, O and H. A first layer of photoresist is formed on the second dielectric layer and a via feature is patterned in the photoresist, wherein the via feature exposes a portion of the second dielectric layer. The substrate is then exposed to a first reactive ion etching process, wherein the first reactive ion etch process anisotropically removes the exposed portion of the second dielectric layer to expose a portion of the first dielectric layer. The substrate is then exposed to a second reactive ion etching process, wherein the second reactive ion etch process anisotropically removes the exposed portion of the first layer to expose a portion of a barrier layer. The first photoresist layer, polymers and post etch residues are stripped from the substrate.
A planar coating of an anti-reflective layer is applied to the substrate and a second photoresist layer is formed on the anti-reflective layer. The second photoresist layer is patterned to form a trench feature, wherein the trench feature exposes a portion of the anti-reflective layer. The substrate is exposed to a third reactive ion etching process to anisotropically partially remove the exposed portion of the anti-reflective layer and further remove a portion of the underlying second layer. The anti-reflective layer, the photoresist, polymers and post etch residues are then stripped from the substrate. The substrate is then exposed to a fourth reactive ion etching process to anisotropically remove the exposed portion of the barrier layer.
The process may further include depositing a seed layer onto the substrate. A copper metal layer is then deposited onto the seed layer; and polished. A second barrier layer is then deposited onto the substrate.
The process for removing the photoresist from the substrate includes exposing the photoresist to a reactive plasma, wherein a gas mixture for forming the plasma consists essentially of ethylene, oxygen and nitrogen; and selectively removing the photoresist layer from the underlying layer, wherein the underlying layer is substantially the same as before exposing the photoresist to the plasma.
The above described and other features are exemplified by the following figures and detailed description.